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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Dual differential 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * TEST_CLK can accept the following input levels: LVCMOS or LVTTL * Maximum FOUT frequency: 700MHz * Maximum FOUT/2 frequency: 350MHz * VCO range: 200MHz to 700MHz * Parallel interface for programming counter and VCO frequency multiplier and dividers * Cycle-to-cycle jitter: 25ps (maximum) * RMS period jitter: TBD * 3.3V supply voltage * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS8432-11 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockSTM Synthesizer and a member of the HiPerClockTM S family of High Performance Clock Solutions from ICS. The ICS8432-11 has a selectable TEST_CLK or crystal inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. Output frequencies up to 700MHz for FOUT and 350MHz for FOUT/2 can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics and the multiple frequency outputs of the ICS8432-11 makes it an ideal clock source for Fiber Channel 1 and 2, and Infiniband applications.
ICS
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT
PIN ASSIGNMENT
XTAL_OUT VCO_SEL nP_LOAD M4 M3 M2 M1 M0
32 31 30 29 28 27 26 25 M5 M6 M7 M8 N0 N1 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VCC FOUT/2 nFOUT/2 VCCO FOUT nFOUT VEE
24 23 22
XTAL_IN TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
ICS8432-11
21 20 19 18 17
MR
FOUT nFOUT FOUT/2 nFOUT/2
VEE
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432CY-11
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1
REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 8 M 28. The frequency out is defined as follows: fOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout/2
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the ICS8432-11. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-11 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on
SERIAL LOADING
S_CLOCK
S_DATA S_LOAD
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
nP_LOAD
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
M, N
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE:
8432CY-11
The NULL timing slot must be observed.
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REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Pullup M divider inputs. Data latched on LOW-to-HIGH transistion of Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels. Pulldown Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. No connect. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels. Core supply pin. Half frequency differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are rset causing the true outputs (FOUTx) to go low and the inver ted outputs (nFOUTx) to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between crystal or test inputs as the PLL reference source. LVCMOS / LVTTL interface levels. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator inputs. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 1 6 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc VEE TEST VCC FOUT/2, nFOUT/2 VCCO FOUT, nFOUT
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL_IN, XTAL_OUT nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
Pulldown Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN
8432CY-11
Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF k k
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REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Inputs
TABLE 3A. PARALLEL
MR H L L nP_LOAD X L
AND
SERIAL MODES FUNCTION TABLE
N X Data Data S_LOAD X X L S_CLOCK X X X S_DATA X X X Conditions Reset. M and N counters reset. Data on M and N inputs passed directly to the M divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked.
M X Data Data
L L L L L
H H H H H
X X X X X
X X X X X
L L H
L L X
Data Data Data X Data
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 200 225 250 275 * * 650 675 M Divide 8 9 10 11 * * 26 27 256 M8 0 0 0 0 * * 0 0 128 M7 0 0 0 0 * * 0 0 64 M6 0 0 0 0 * * 0 0 32 M5 0 0 0 0 * * 0 0 16 M4 0 0 0 0 * * 1 1 8 M3 1 1 1 1 * * 1 1 4 M2 0 0 0 0 * * 0 0 2 M1 0 0 1 1 * * 1 1 1 M0 0 1 0 1 * * 0 1 0
700 28 0 0 0 0 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1
8432CY-11
Output Frequency (MHz) N Divider Value N0 0 1 0 1 1 2 4 8 Minimum 200 100 50 25 FOUT Maximum 70 0 350 175 87.5 FOUT/2 Minimum Maximum 125 62.5 31.25 15.625 350 175 87.5 43.75
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 110 15 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, Input S_DATA, S_LOAD, nP_LOAD High Current M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 TEST; NOTE 1 Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A
IIH
IIL
Input Low Current
-150 2. 6 0.5
A V V
NOTE 1: Outputs terminated with 50 to VCCO/2. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit" figure.
8432CY-11
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE 1 12 25 MHz XTAL_IN, XTAL_OUT; Input Frequency 12 25 MHz fIN NOTE 1 S_CLOCK TBD MHz NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 200MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 17 M 58. Using the maximum frequency of 25MHz, valid values of M are 8 M 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 12 Test Conditions Minimum Typical Maximum 25 70 7 1 Units MHz pF mW Fundamental
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol FOUT tjit(cc) tjit(per) Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 3 Period Jitter, RMS; NOTE 1, 3 Output Skew; NOTE 2, 3 Output Rise Time Output Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle 20% to 80% @ 50MHz 20% to 80% @ 50MHz 30 0 30 0 5 5 5 5 5 5 47 53 10 Test Conditions Minimum 25 Typical Maximum 700 25 TBD TBD 700 700 Units MHz ps ps ps ps ps ns ns ns ns ns ns % ms
tsk(o)
tR tF
PLL Lock Time tLOCK All parameters measured at 500MHz unless noted otherwise. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8432CY-11
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Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VOH
V CC , VCCA, VCCO
Qx
SCOPE
VREF VOL
LVPECL
VEE
nQx
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
Histogram
-1.3V 0.165V
(Trigger Edge)
Mean Period
(First edge after trigger)
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nFOUT FOUT nFOUT, nFOUT/2 FOUT, FOUT/2
nFOUT/2 FOUT/2
tsk(o)
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nFOUT, nFOUT/2 80% FOUT, FOUT/2 80% VSW I N G
t
PERIOD
t PW
Clock Outputs
20% tR tF
odc =
t PW t PERIOD
x 100%
OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
8432CY-11
OUTPUT RISE/FALL TIME
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tcycle n+1
20%
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATIONS
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application frequencies as well as the ICS8432-11 configurations used to generate the appropriate frequency.
Table 8. COMMON SANS APPLICATIONS FREQUENCIES
Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Clock Rate 1.25 GHz FC1 1.0625 GHz FC2 2.1250 GHz 2.5 GHz Reference Frequency to SERDES (MHz) 125, 250, 156.25 106.25, 53.125, 132.8125 125, 250 Crystal Frequency (MHz) 25, 19.53125 16.6015625, 25 25
Table 9. CONFIGURATION DETAILS
Interconnect Technology
FOR
SANS APPLICATIONS
ICS8432-11 Output Frequency to SERDES (MHz) 125 250 156.25 156.25 53.125 106.25 132.8125 125 250 ICS8432-11 M & N Settings M8 M7 M6 M5 M4 M3 M2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 M1 M0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 N1 1 0 1 1 1 1 1 1 0 N0 0 1 0 0 1 0 0 0 1
Crystal Frequency (MHz) 25 25
Gigabit Ethernet 25 19.53125 25 Fiber Channel 1 25 Fiber Channel 2 Infiniband 25 16.6015625 25
8432CY-11
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ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION
FOR
LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
out in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8432-11 layout example used in this layout guideline is shown in Figure 4A. The ICS8432-11 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The lay-
C1 X1 32 31 30 29 28 27 26 25
C2
U1
9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16
ICS8432-11
TEST VCC FOUT/2 nFOUT/2 VCCO FOUT nFOUT VEE
1 2 3 4 5 6 7 8
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_OUT
VCC 24 23 22 21 20 19 18 17 R7 10 VCCA S_LOAD S_DATA S_CLOCK C11 0.01u C16 10u
M5 M6 M7 M8 N0 N1 nc VEE
X_IN T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
REF_IN XTAL_SEL
VCC
VCC
R1 125 Zo = 50 Ohm IN+ TL1
R3 125
C14 0.1u C15 0.1u Zo = 50 Ohm
+ IN-
TL2
-
VCC=3.3V
R2 84
R4 84
FIGURE 4A. SCHEMATIC
OF
RECOMMENDED LAYOUT
8432CY-11
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ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
* The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a spearation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 24 (XTAL_IN) and 25 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
X1
GND VCC VIA
U1
PIN 1
C11 C16 VCCA R7 Close to the input pins of the receiver R4 R3 TL1N
TL1N
C15 C14
TL1 R2
TL1 TL1, TL2 are 50 Ohm traces and equal length
R1
FIGURE 4B. PCB BOARD LAYOUT
8432CY-11
FOR
ICS8432-11
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Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-11. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8432-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 10 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.441W * 42.1C/W = 88.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 10. THERMAL RESISTANCE
JA FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432CY-11
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12
REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
- 1.0V
(VCCO_MAX - VOH_MAX) = 1.0V * For logic low, VOUT = V (V
CCO_MAX
OL_MAX
=V
CCO_MAX
- 1.7V
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50) * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8432CY-11
www.icst.com/products/hiperclocks.html
13
REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 11. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-11 is: 3765
8432CY-11
www.icst.com/products/hiperclocks.html
14
REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 12. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8432CY-11
www.icst.com/products/hiperclocks.html
15
REV. E MAY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8432-11
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432CY-11 ICS8432CY-11 Package 32 Lead LQFP 32 Lead LQFP Shipping Packaging tray 1000 tape & reel Temperature 0C to 70C 0C to 70C
TABLE 13. ORDERING INFORMATION
Part/Order Number ICS8432CY-11 ICS8430CY-11T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432CY-11
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16
REV. E MAY 20, 2005

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